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/Method Of Manufacturing In A Compute-in-memory System Having Bit Error Detection, And Method Of Operating Same
Abstract

A method (of operating compute-in-memory memory (CIM) system) includes: for first groups each of which including a multiplier and a first bit-error detector, the CIM system including (in a first region of a semiconductor die) an array memory cells configured to store first bits, an array of multipliers and first bit-error detectors, a first array memory cells arranged in first rows and first columns, the first array being configured to store first words; second ones of the memory cells being arranged in a second array configured to store parity bits corresponding to the first bits: performing generation of the first words by performing one or more multiplications of (A) input words and associated first checksum words and (B) corresponding weight words and associated second checksum words, and performing generation a row-based bit-error locus-inferable signal or a column-based bit-error locus-inferable signal based on selected ones of the first words.

Full Text

What is claimed is:

A method (of operating compute-in-memory memory (CIM) system) includes: for first groups each of which including a multiplier and a first bit-error detector, the CIM system including (in a first region of a semiconductor die) an array memory cells configured to store first bits, an array of multipliers and first bit-error detectors, a first array memory cells arranged in first rows and first columns, the first array being configured to store first words; second ones of the memory cells being arranged in a second array configured to store parity bits corresponding to the first bits: performing generation of the first words by performing one or more multiplications of (A) input words and associated first checksum words and (B) corresponding weight words and associated second checksum words, and performing generation a row-based bit-error locus-inferable signal or a column-based bit-error locus-inferable signal based on selected ones of the first words.
Timeline
Filed
02/19/2026
Published
06/25/2026
Granted
Not Available
IPC Codes(2)
G06F 11/10:Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/07:Responding to the occurrence of a fault, e.g. fault tolerance