Abstract
A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.
Full Text
What is claimed is:
A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.
Timeline
Filed
02/18/2026Published
06/25/2026Granted
Not AvailableIPC Codes(8)
H10W 40/40:involving heat exchange by flowing fluids
H10W 20/20:Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
H10W 72/00:Interconnections or connectors in packages