Examples of the present disclosure disclose a memory device and an operation method thereof, and related structures. An interface of the memory device includes a first circuit and is configured to: receive a first operation command and a second operation command, wherein the first operation command is to indicate to perform a first operation on the memory device, the second operation command is to indicate to turn off the first circuit in the memory device, and the first circuit includes a circuit that may not be used when the first operation is performed on the memory device; and receive a third operation command, wherein the third operation command is to indicate to turn on the first circuit.