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/Semiconductor Device Including A Vertical Channel Transistor With A Back Gate Electrode
Abstract

A semiconductor device includes a first semiconductor chip including a bit line, a vertical channel transistor electrically connected to the bit line, a capacitor electrically connected to the vertical channel transistor, and first bonding pads electrically connected to the bit line, and a second semiconductor chip including a peripheral circuit and a plurality of second bonding pads electrically connected to the peripheral circuit. The vertical channel transistor includes a back gate electrode, first and second active patterns disposed on opposite sides of the back gate electrode, respectively, and first and second word lines disposed on respective sidewalls of the first and second active patterns facing away from the back gate electrode. The first semiconductor chip is stacked on and directly bonded to the second semiconductor chip such that the first bonding pads are respectively directly bonded to corresponding ones of the second bonding pads.

Full Text

What is claimed is:

A semiconductor device includes a first semiconductor chip including a bit line, a vertical channel transistor electrically connected to the bit line, a capacitor electrically connected to the vertical channel transistor, and first bonding pads electrically connected to the bit line, and a second semiconductor chip including a peripheral circuit and a plurality of second bonding pads electrically connected to the peripheral circuit. The vertical channel transistor includes a back gate electrode, first and second active patterns disposed on opposite sides of the back gate electrode, respectively, and first and second word lines disposed on respective sidewalls of the first and second active patterns facing away from the back gate electrode. The first semiconductor chip is stacked on and directly bonded to the second semiconductor chip such that the first bonding pads are respectively directly bonded to corresponding ones of the second bonding pads.
Timeline
Filed
02/18/2026
Published
06/25/2026
Granted
Not Available
IPC Codes(4)
H10B 80/00:Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10B 12/00:Dynamic random access memory [DRAM] devices
H10W 80/00:Direct bonding of chips, wafers or substrates