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/Via Alternate Net Spacing
Abstract

A chip includes a first net, and a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net. The chip also includes first vias disposed on the first net, and second vias disposed on the second net. A first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias.

Full Text

What is claimed is:

A chip includes a first net, and a second net, wherein the first net and the second net are formed from a same metal layer, and the second net neighbors the first net. The chip also includes first vias disposed on the first net, and second vias disposed on the second net. A first spacing is greater than a second spacing, the first spacing is between a first one of the first vias and a second one of the first vias, the first one of the first vias and the second one of the first vias are adjacent, and the second spacing is between the first one of the first vias and one of the second vias closest to the first one of the first vias.
Timeline
Filed
02/19/2026
Published
06/25/2026
Granted
Not Available
IPC Codes(2)
H10D 64/23:Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27:Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates