A method of manufacturing a semiconductor device includes providing a stack including interlayer sacrifice layers and interlayer insulation layers stacked alternatively. The stack includes a core region and a periphery region distributed along a first direction. The method also includes forming a gate line slit penetrating the stack and extending along the first direction. The gate line slit includes a first slit and a second slit interconnected with each other. The periphery region includes the first slit. The core region includes the second slit. The width of the first slit along the second direction is greater than the width of the second slit along the second direction. The second direction intersects with the first direction. The method further includes forming an isolation section in at least the first slit.