A computing apparatus is disclosed, including a scheduling module, an interrupt controller, and at least one processor core. The scheduling module is configured to schedule N tasks. The interrupt controller is configured to schedule M interrupts. The N tasks and the M interrupts are marked by using unified priorities, one task corresponds to one priority, and one interrupt corresponds to one priority. A target processor core in the at least one processor core is configured to: receive and run a target task sent by the scheduling module, where the target task is one of the N tasks; and receive a target interrupt sent by the interrupt controller, and if a priority corresponding to the target interrupt is lower than or equal to a priority corresponding to the target task, continue to run the target task, where the target interrupt is one of the M interrupts.