A semiconductor device includes a memory cell wafer. The memory cell wafer includes a dielectric layer, a conductor layer over the dielectric layer, one or more through contacts penetrating through the dielectric layer and the conductor layer, and an isolator surrounding a region of the conductor layer and at least one of the one or more through contacts in a horizontal direction and extending vertically through the conductor layer to be connected to the dielectric layer. The region of the conductor layer surrounded by the isolator is isolated from other portions of the conductor layer. Each of the one or more through contacts includes a column part in the dielectric layer and a pad part in the conductor layer.