A semiconductor storage device includes a memory string, a sense amplifier including first and second latch circuits, a cache memory including a third latch circuit, and a control circuit. The control circuit is configured to perform a first read operation in response to a first command set and consecutively perform a second read operation in response to a second command set received during the first read operation. During the first read operation, data read from the memory string is stored in the first latch circuit. When the second command set is received at a first timing, the control circuit transfers the data to the second latch circuit, and then to the third latch circuit. When the second command set is received at a second timing before the first timing, the control circuit directly transfers the data to the third latch circuit.