Abstract
A semiconductor device including an input circuit including a buffer configured to buffer an external signal that is received from a pad, a variable delay circuit configured to delay a signal that is output by the buffer in response to a plurality of delay setting signals, and a latch configured to output the output of the variable delay circuit as an internal signal by latching the output in response to a clock signal, and a setting circuit configured to store the plurality of delay setting signals.
Full Text
What is claimed is:
A semiconductor device including an input circuit including a buffer configured to buffer an external signal that is received from a pad, a variable delay circuit configured to delay a signal that is output by the buffer in response to a plurality of delay setting signals, and a latch configured to output the output of the variable delay circuit as an internal signal by latching the output in response to a clock signal, and a setting circuit configured to store the plurality of delay setting signals.
Timeline
Filed
02/25/2026Published
07/02/2026Granted
Not AvailableIPC Codes(3)
G11C 7/10:Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/14:Dummy cell management; Sense reference voltage generators
G11C 7/22:Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management