Abstract
A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.
Full Text
What is claimed is:
A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.
Timeline
Filed
02/25/2026Published
07/02/2026Granted
Not AvailableIPC Codes(10)
H10W 40/22:characterised by their shape, e.g. having conical or cylindrical projections
H10W 20/43:Layouts of interconnections
H10W 72/00:Interconnections or connectors in packages