Abstract
This disclosure describes a novel .method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
Full Text
What is claimed is:
This disclosure describes a novel .method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.
Timeline
Filed
02/27/2026Published
07/02/2026Granted
Not AvailableIPC Codes(4)
G01R 31/3177:Testing of logic operation, e.g. by logic analysers
G01R 31/26:Testing of individual semiconductor devices (testing or measuring during manufacture or treatment H10P 74/00; testing of photovoltaic devices H02S 50/10)
G01R 31/317:Testing of digital circuits