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/Semiconductor Package Structure And Packaging Method Thereof, And Electronic Device
Abstract

The semiconductor package structure includes: a substrate, and a first chip and a second chip that are stacked on the substrate, where the first chip is located between the substrate and the second chip; a filling part, surrounding a side face of the first chip and a side face of the second chip, and being continuous in a direction perpendicular to the substrate; and a support ring, where an orthographic projection of the support ring on the substrate surrounds an orthographic projection of the first chip on the substrate, the support ring is embedded in the filling part, and is located on a side that is of a first reference plane and that is close to the substrate, and the first reference plane is a plane on which a surface that is of the second chip and that is close to the first chip is located.

Full Text

What is claimed is:

The semiconductor package structure includes: a substrate, and a first chip and a second chip that are stacked on the substrate, where the first chip is located between the substrate and the second chip; a filling part, surrounding a side face of the first chip and a side face of the second chip, and being continuous in a direction perpendicular to the substrate; and a support ring, where an orthographic projection of the support ring on the substrate surrounds an orthographic projection of the first chip on the substrate, the support ring is embedded in the filling part, and is located on a side that is of a first reference plane and that is close to the substrate, and the first reference plane is a plane on which a surface that is of the second chip and that is close to the first chip is located.
Timeline
Filed
02/27/2026
Published
07/02/2026
Granted
Not Available
IPC Codes(7)
H10W 90/22:the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
H10W 42/00:Arrangements for protection of devices (arrangements for thermal protection H10W 40/00)
H10W 70/08:by depositing layers on the chip or wafer, e.g. "chip-first" RDLs