Abstract
The semiconductor structure includes a substrate defined with an array region and a seal ring region surrounding the array region, and including a recess extending into the substrate; a capacitor cell disposed within the array region; and a seal ring disposed within the seal ring region, and including a capacitor structure at least partially disposed within the recess, and an interconnect structure disposed over the capacitor structure, wherein the interconnect structure is electrically coupled to the substrate.
Full Text
What is claimed is:
The semiconductor structure includes a substrate defined with an array region and a seal ring region surrounding the array region, and including a recess extending into the substrate; a capacitor cell disposed within the array region; and a seal ring disposed within the seal ring region, and including a capacitor structure at least partially disposed within the recess, and an interconnect structure disposed over the capacitor structure, wherein the interconnect structure is electrically coupled to the substrate.
Timeline
Filed
03/06/2026Published
07/09/2026Granted
Not AvailableIPC Codes(3)
H10W 42/00:Arrangements for protection of devices (arrangements for thermal protection H10W 40/00)
H10D 1/00:Resistors, capacitors or inductors
H10D 1/68:Capacitors having no potential barriers