Provided is a display device including a pixel array including a plurality of pixels arranged in a matrix. Each pixel includes a pulse width modulation (PWM) circuit and an emission device; a data driver configured to provide pixel data to pixels arranged in a row of the pixel array; and a row driver configured to generate control signals and clock signals for driving the pixel array. The PWM circuit is configured to generate the PWM signal based on the control signals and the clock signals, the PWM signal including a plurality of bit fields respectively corresponding to a plurality of bits of the pixel data. The PWM circuit is further configured to, in a PWM period in which the PWM signal is output, distribute a first bit field of the PWM signal corresponding to a most significant bit (MSB) of the pixel data, among the plurality of bit fields.