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/Gate Spacers In Semiconductor Devices
Abstract

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, forming a superlattice structure including first and second nanostructured layers on the fin base, forming a polysilicon structure on the superlattice structure, epitaxially growing a S/D region on the fin base and adjacent to the first nanostructured layer, forming an oxygen-rich outer gate spacer including a first dielectric material with a first non-stoichiometric composition on a sidewall of the polysilicon structure, forming an oxygen-rich inner gate spacer including a second dielectric material with a second non-stoichiometric composition on a sidewall of the second nanostructured layer, and replacing the polysilicon structure with a gate structure.

Full Text

What is claimed is:

A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin base on a substrate, forming a superlattice structure including first and second nanostructured layers on the fin base, forming a polysilicon structure on the superlattice structure, epitaxially growing a S/D region on the fin base and adjacent to the first nanostructured layer, forming an oxygen-rich outer gate spacer including a first dielectric material with a first non-stoichiometric composition on a sidewall of the polysilicon structure, forming an oxygen-rich inner gate spacer including a second dielectric material with a second non-stoichiometric composition on a sidewall of the second nanostructured layer, and replacing the polysilicon structure with a gate structure.
Timeline
Filed
03/05/2026
Published
07/09/2026
Granted
Not Available
IPC Codes(6)
H10D 64/01:Manufacture or treatment
H10D 30/01:Manufacture or treatment
H10D 30/43:having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels