Abstract
A memory interface circuit includes an instruction decoder configured to receive an instruction from a processor to generate a corresponding control code. An execution circuit is configured to receive the control code from the instruction decoder and access a memory and generate an arithmetic result according to the control code
Full Text
What is claimed is:
A memory interface circuit includes an instruction decoder configured to receive an instruction from a processor to generate a corresponding control code. An execution circuit is configured to receive the control code from the instruction decoder and access a memory and generate an arithmetic result according to the control code
Timeline
Filed
03/05/2026Published
07/09/2026Granted
Not AvailableIPC Codes(3)
G06F 9/30:Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F 9/22)
G06F 3/06:Digital input from, or digital output to, record carriers
G06F 7/575:Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry