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/Ferroelectric Tunnel Junction Structure With L-shaped Spacers
Abstract

A ferroelectric tunnel junction (FTJ) includes bottom and top electrodes and a ferroelectric layer disposed between the bottom and top electrodes. A dielectric material is disposed in a space between a peripheral area of the ferroelectric layer and a sidewall of the top electrode. At least one conformal dielectric spacer is deposited. The FTJ is annealed to induce ferroelectric phase crystallization in the ferroelectric layer. The depositing at least one conformal dielectric spacer includes at least one of: (i) prior to the disposing of the dielectric material, depositing an inner conformal dielectric spacer on the peripheral area of the ferroelectric layer and on the sidewall of the top electrode, and/or (ii) after the disposing of the dielectric material, depositing an outer conformal dielectric spacer on dielectric material and on a sidewall of the peripheral area of the ferroelectric layer.

Full Text

What is claimed is:

A ferroelectric tunnel junction (FTJ) includes bottom and top electrodes and a ferroelectric layer disposed between the bottom and top electrodes. A dielectric material is disposed in a space between a peripheral area of the ferroelectric layer and a sidewall of the top electrode. At least one conformal dielectric spacer is deposited. The FTJ is annealed to induce ferroelectric phase crystallization in the ferroelectric layer. The depositing at least one conformal dielectric spacer includes at least one of: (i) prior to the disposing of the dielectric material, depositing an inner conformal dielectric spacer on the peripheral area of the ferroelectric layer and on the sidewall of the top electrode, and/or (ii) after the disposing of the dielectric material, depositing an outer conformal dielectric spacer on dielectric material and on a sidewall of the peripheral area of the ferroelectric layer.
Timeline
Filed
03/05/2026
Published
07/09/2026
Granted
Not Available
IPC Codes(4)
H10B 51/30:characterised by the memory core region
H10D 30/01:Manufacture or treatment
H10D 30/69:IGFETs having charge trapping gate insulators, e.g. MNOS transistors