Abstract
A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.
Full Text
What is claimed is:
A memory cell includes a bottom electrode, a storage element layer, a first buffer layer, and a top electrode. The storage element layer is disposed over the bottom electrode. The first buffer layer is interposed between the storage element layer and the bottom electrode, where a thermal conductivity of the first buffer layer is less than a thermal conductivity of the storage element layer. The top electrode is disposed over the storage element layer, where the storage element layer is disposed between the top electrode and the first buffer layer.
Timeline
Filed
03/12/2026Published
07/16/2026Granted
Not AvailableIPC Codes(4)
H10N 70/20:Multistable switching devices, e.g. memristors
H10B 63/10:Phase change RAM [PCRAM, PRAM] devices
H10N 70/00:Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching (integrated devices or assemblies of multiple devices H10N 79/00)