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/Semiconductor Device Structure With Metal Gate Stack
Abstract

A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a first semiconductor fin and multiple second semiconductor nanostructures stacked in a first direction over a second semiconductor fin. A topmost second semiconductor nanostructure of the second semiconductor nanostructures is thinner than one or more of lower semiconductor nanostructures of the second semiconductor nanostructures in the first direction. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure. The semiconductor device structure further includes a first metal gate stack wrapped around the first semiconductor nanostructures and a second metal gate stack wrapped around the second semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure laterally surrounding a lower portion of the second semiconductor fin. An upper portion of the second semiconductor fin is laterally surrounded by the second metal gate stack.

Full Text

What is claimed is:

A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a first semiconductor fin and multiple second semiconductor nanostructures stacked in a first direction over a second semiconductor fin. A topmost second semiconductor nanostructure of the second semiconductor nanostructures is thinner than one or more of lower semiconductor nanostructures of the second semiconductor nanostructures in the first direction. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure. The semiconductor device structure further includes a first metal gate stack wrapped around the first semiconductor nanostructures and a second metal gate stack wrapped around the second semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure laterally surrounding a lower portion of the second semiconductor fin. An upper portion of the second semiconductor fin is laterally surrounded by the second metal gate stack.
Timeline
Filed
03/12/2026
Published
07/16/2026
Granted
Not Available
IPC Codes(3)
H10D 30/01:Manufacture or treatment
H10D 30/62:Fin field-effect transistors [FinFET]
H10D 64/01:Manufacture or treatment