A memory device includes a first lower semiconductor layer and a second lower semiconductor layer. The first lower semiconductor layer is disposed below a first upper semiconductor layer including a first memory cell array. The first lower semiconductor layer includes a first page buffer electrically connected to the first memory cell array. The second lower semiconductor layer is disposed below a second upper semiconductor layer includes a second memory cell array and disposed adjacent to the first upper semiconductor layer in a first direction. The second lower semiconductor layer includes a first portion of a second page buffer electrically connected to the second memory cell array and being disposed adjacent to the first lower semiconductor layer in the first direction. The first lower semiconductor layer further includes a second portion of the second page buffer different from the first portion.