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/Method Of Manufacturing Semiconductor Structure
Abstract

A method of manufacturing a semiconductor structure is provided by embodiments of this disclosure, and the method includes the following steps. An insulating area and an active area are formed in a substrate. A first word line trench is formed in the active are. A first dielectric layer is deposited in the first word line trench and on the active area and the insulating area. A second word line trench is formed through etching the first dielectric layer. Besides, the second word line trench is linear and extends through the insulating area and the active area of the substrate, and a portion of the first dielectric layer is remained in a bottom of the second word line trench. Then, a word line structure is formed in the second word line trench. Moreover, a semiconductor structure is provided in this disclosure.

Full Text

What is claimed is:

A method of manufacturing a semiconductor structure is provided by embodiments of this disclosure, and the method includes the following steps. An insulating area and an active area are formed in a substrate. A first word line trench is formed in the active are. A first dielectric layer is deposited in the first word line trench and on the active area and the insulating area. A second word line trench is formed through etching the first dielectric layer. Besides, the second word line trench is linear and extends through the insulating area and the active area of the substrate, and a portion of the first dielectric layer is remained in a bottom of the second word line trench. Then, a word line structure is formed in the second word line trench. Moreover, a semiconductor structure is provided in this disclosure.
Timeline
Filed
03/12/2026
Published
07/16/2026
Granted
Not Available
IPC Codes(3)
H10W 20/00:Interconnections in chips, wafers or substrates
H10P 50/00:Etching of wafers, substrates or parts of devices
H10W 20/43:Layouts of interconnections