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/Architecture And Method For Nand Memory Operation
Abstract

In a method for programming a memory cell string, a programming voltage is applied on a selected word line to program a selected memory cell of the memory cell string. A first pass voltage is applied on a first word line coupled to a first memory cell of the memory cells. A second pass voltage is applied on a second word line coupled to a second memory cell of the memory cells. Further, a third pass voltage is applied on a third word line coupled to a third memory cell of the memory cells. The first, second and third memory cells are located at a first side of the selected memory cell in the memory cell string, and the second memory cell is disposed between the first memory cell and the third memory cell. The second pass voltage is higher than the first pass voltage and the third pass voltage.

Full Text

What is claimed is:

In a method for programming a memory cell string, a programming voltage is applied on a selected word line to program a selected memory cell of the memory cell string. A first pass voltage is applied on a first word line coupled to a first memory cell of the memory cells. A second pass voltage is applied on a second word line coupled to a second memory cell of the memory cells. Further, a third pass voltage is applied on a third word line coupled to a third memory cell of the memory cells. The first, second and third memory cells are located at a first side of the selected memory cell in the memory cell string, and the second memory cell is disposed between the first memory cell and the third memory cell. The second pass voltage is higher than the first pass voltage and the third pass voltage.
Timeline
Filed
03/13/2026
Published
07/16/2026
Granted
Not Available
IPC Codes(3)
G11C 16/10:Programming or data input circuits
G11C 16/04:using variable threshold transistors, e.g. FAMOS
G11C 16/08:Address circuits; Decoders; Word-line control circuits