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/Semiconductor Device And Method Of Forming The Same
Abstract

A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.

Full Text

What is claimed is:

A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.
Timeline
Filed
03/16/2026
Published
07/16/2026
Granted
Not Available
IPC Codes(7)
H10D 62/13:Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 30/01:Manufacture or treatment
H10D 30/43:having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels