Abstract
A method for manufacturing a power device. The power device includes an electrical substrate, an epitaxial layer, a well region, a plurality of doping regions, a plurality of trenches, a first oxidation layer, a second oxidation layer, a polycrystalline silicon filler, two shielding regions, a dielectric layer, and a metallic electrically conductive layer.
Full Text
What is claimed is:
A method for manufacturing a power device. The power device includes an electrical substrate, an epitaxial layer, a well region, a plurality of doping regions, a plurality of trenches, a first oxidation layer, a second oxidation layer, a polycrystalline silicon filler, two shielding regions, a dielectric layer, and a metallic electrically conductive layer.
Timeline
Filed
03/16/2026Published
07/16/2026Granted
Not AvailableIPC Codes(8)
H10D 84/00:Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 12/01:Manufacture or treatment
H10D 30/66:Vertical DMOS [VDMOS] FETs