A semiconductor memory device includes a substrate including a first region and a second region, the first region includes a peripheral circuit, a first active region (FAR), a second active region (SAR), and a third active region (TAR); the second region includes memory cell blocks; a first pass transistor circuit in the FAR and configured to transmit driving signals such that operating voltages are applied to the memory cell blocks; a second pass transistor circuit in the SAR; and a third pass transistor circuit in the TAR, the first pass transistor circuit includes FAR first, second and third gate structure, and a first shared source/drain, the second pass transistor circuit includes SAR first, second and third gate structures, and a second shared source/drain, and the third pass transistor circuit includes TAR first, second and third gate structures, and a third shared source/drain.