A semiconductor device structure is provided. The structure includes a source/drain feature and a first insulating layer over the active region over a substrate, an isolation feature disposed alongside the active region, first and second gate spacers in the first insulating layer. A portion of the source/drain feature overhangs the isolation feature. The structure also includes an insulating feature adjacent to the second gate spacer and a first conductive gate stack including a gate electrode layer and an overlying conductive capping layer that are adjacent to the first gate spacer, and a first gate dielectric layer that is between the first spacer and both of the gate electrode layer and the conductive capping layer and has an upper surface that is substantially level with an upper surface of the first gate spacer and protrudes above an upper surface of the gate electrode layer.
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What is claimed is: