Abstract
A SiC semiconductor device includes a SiC chip having a main surface that includes a first surface, a second surface hollowed in a thickness direction outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a trench structure formed at the first surface such as to be exposed from the connecting surface, and a sidewall wiring that is formed on the second surface such as to cover the connecting surface and that is electrically connected to the trench structure.
Full Text
What is claimed is:
A SiC semiconductor device includes a SiC chip having a main surface that includes a first surface, a second surface hollowed in a thickness direction outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a trench structure formed at the first surface such as to be exposed from the connecting surface, and a sidewall wiring that is formed on the second surface such as to cover the connecting surface and that is electrically connected to the trench structure.
Timeline
Filed
03/19/2026Published
07/23/2026Granted
Not AvailableIPC Codes(4)
H10D 62/832:being Group IV materials comprising two or more elements, e.g. SiGe
H10D 30/66:Vertical DMOS [VDMOS] FETs
H10D 62/10:Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies