AI processors integrate dense arrays of processing cores alongside memory controllers and interconnect fabric, where every square millimeter of silicon carries both cost and yield implications. Some implementations of a modified processing unit (MxPU) include a silicon die having processing cores coupled via a coherent interconnect, memory channels for communicating with external memory, and a repurposed area occupying a space equivalent to at least one processing core. The repurposed area, originally designed to accommodate at least one processing core, instead accommodates at least one of a communication port or a resource provisioning unit (RPU). The communication port is selected from a CXL endpoint, a CXL switch port, an NVLink port, or a UALink port, and receives messages comprising physical addresses within a second physical address space. The RPU translates those physical addresses to a first physical address space utilized by the processing cores.