/Processing Element Scheduling Apparatus And Method, Chip, And Related Device
Abstract

Embodiments of this application provide example processing element scheduling apparatuses, methods, chips, and related devices. One example processing element (PE) scheduling apparatus includes a first arbiter and M PEs connected to the first arbiter, where M is a positive integer greater than or equal to 2. Each PE is configured to send a first request signal to the first arbiter, where the first request signal is used to request to switch the corresponding PE from a first power state to a second power state, and a power in the first power state is lower than a power in the second power state. The first arbiter is configured to receive one or more first request signals sent by one or more PEs of the M PEs, perform arbitration to obtain a first response sequence of the one or more first request signals.

Full Text

What is claimed is:

Embodiments of this application provide example processing element scheduling apparatuses, methods, chips, and related devices. One example processing element (PE) scheduling apparatus includes a first arbiter and M PEs connected to the first arbiter, where M is a positive integer greater than or equal to 2. Each PE is configured to send a first request signal to the first arbiter, where the first request signal is used to request to switch the corresponding PE from a first power state to a second power state, and a power in the first power state is lower than a power in the second power state. The first arbiter is configured to receive one or more first request signals sent by one or more PEs of the M PEs, perform arbitration to obtain a first response sequence of the one or more first request signals.
Timeline
Filed
03/19/2026
Published
07/23/2026
Granted
Not Available
IPC Codes(2)
G06F 9/48:Program initiating; Program switching, e.g. by interrupt
G06F 11/34:Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation