/Linear To Physical Address Translation With Support For Page Attributes
Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Full Text

What is claimed is:

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
Timeline
Filed
03/30/2026
Published
07/23/2026
Granted
Not Available
IPC Codes(4)
G06F 12/1009:using page tables, e.g. page table structures
G06F 12/10:Address translation
G06F 12/1027:using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]