Abstract
An apparatus includes: a memory controller comprising a data interface and a read data strobe input; a first memory device and a second memory device, each having respective data lines coupled to the data interface of the memory controller; and a read data strobe line coupling a read data strobe output of one of the first and second memory devices to the read data strobe input of the memory controller, wherein the memory controller is configured to sample data received from both the first memory device and the second memory device based on a read data strobe signal received at the read data strobe input.
Full Text
What is claimed is:
An apparatus includes: a memory controller comprising a data interface and a read data strobe input; a first memory device and a second memory device, each having respective data lines coupled to the data interface of the memory controller; and a read data strobe line coupling a read data strobe output of one of the first and second memory devices to the read data strobe input of the memory controller, wherein the memory controller is configured to sample data received from both the first memory device and the second memory device based on a read data strobe signal received at the read data strobe input.
Timeline
Filed
03/26/2026Published
07/30/2026Granted
Not AvailableIPC Codes(2)
G11C 7/10:Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22:Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management