A memory device includes a memory cell array that includes a plurality of memory cells, an input/output circuit configured to transmit data received from an external source through a data pad to the memory cell array or transmit data read from the memory cell array to the external source, and an impedance calibration circuit configured to generate an impedance calibration code that is applied to the input/output circuit, the impedance calibration circuit is further configured to: divide a total impedance calibration section into a plurality of sub-impedance calibration sections, and perform at least one sub-impedance calibration in each of the plurality of sub-impedance calibration sections, the at least one sub-impedance calibration corresponding to at least one of a plurality of impedance modes.