/Semiconductor Device Including A Self-aligned Contact Layer With Enhanced Etch Resistance
Abstract

A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-aligned contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.

Full Text

What is claimed is:

A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-aligned contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.
Timeline
Filed
03/26/2026
Published
07/30/2026
Granted
Not Available
IPC Codes(7)
H10W 20/00:Interconnections in chips, wafers or substrates
H10D 30/01:Manufacture or treatment
H10D 30/62:Fin field-effect transistors [FinFET]