Abstract
An integrated circuit system includes software-programmable vector processing circuitry having software-programmable vector processors arranged in processing nodes in an array. Each of the processing nodes is communicatively coupled to adjacent ones of the processing nodes in the array through a mesh router. Each of the software-programmable vector processors comprises processing elements. Each of the processing elements is capable of processing first data in a floating point data format. Each of the processing elements is capable of processing integer data. The processing elements comprise hardened circuits that are capable of executing instructions and providing processed data in response to the instructions.
Full Text
What is claimed is:
An integrated circuit system includes software-programmable vector processing circuitry having software-programmable vector processors arranged in processing nodes in an array. Each of the processing nodes is communicatively coupled to adjacent ones of the processing nodes in the array through a mesh router. Each of the software-programmable vector processors comprises processing elements. Each of the processing elements is capable of processing first data in a floating point data format. Each of the processing elements is capable of processing integer data. The processing elements comprise hardened circuits that are capable of executing instructions and providing processed data in response to the instructions.
Timeline
Filed
03/27/2026Published
07/30/2026Granted
Not AvailableIPC Codes(6)
G06F 15/80:comprising an array of processing units with common control, e.g. single instruction multiple data processors (takes precedence G06F 15/82)
G06F 9/30:Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F 9/22)
G06F 9/38:Concurrent instruction execution, e.g. pipeline or look ahead