/Systems, Devices And Methods With Offload Processing Devices
Abstract

A method for accelerating computing applications with bus compatible modules can include receiving network packets that include data for processing, the data being a portion of a larger data set processed by an application; evaluate header information of the network packets to map network packets to any of a plurality of destinations on the first module, each destination corresponding to at least one of a plurality of offload processors of the first module; executing a programmed operation of the application in parallel on multiple offload processors to generate first processed application data; and transport the first processed application data out of the first module. Corresponding systems and devices are also disclosed.

Full Text

What is claimed is:

A method for accelerating computing applications with bus compatible modules can include receiving network packets that include data for processing, the data being a portion of a larger data set processed by an application; evaluate header information of the network packets to map network packets to any of a plurality of destinations on the first module, each destination corresponding to at least one of a plurality of offload processors of the first module; executing a programmed operation of the application in parallel on multiple offload processors to generate first processed application data; and transport the first processed application data out of the first module. Corresponding systems and devices are also disclosed.
Timeline
Filed
03/26/2026
Published
07/30/2026
Granted
Not Available
IPC Codes(10)
H04L 47/2441:relying on flow classification, e.g. using integrated services [IntServ]
G06F 13/16:for access to memory bus (takes precedence G06F 13/28)
G06F 13/28:using burst mode transfer, e.g. direct memory access, cycle steal (takes precedence G06F 13/32)