Abstract
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
Full Text
What is claimed is:
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
Timeline
Filed
03/26/2026Published
07/30/2026Granted
Not AvailableIPC Codes(5)
H10D 12/00:Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 12/01:Manufacture or treatment
H10D 62/10:Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies