Abstract
A semiconductor memory device of the technology, including: a lower structure; a first stacked structure; and a second stacked structure, wherein the first stacked structure includes at least one lower cell plug pattern extending in a vertical direction and a lower slit pattern extending in the vertical direction, and wherein the first stacked structure further includes: a first conductive pattern; a second conductive pattern over the first conductive pattern, wherein the second conductive pattern includes a first portion and a second portion; and a contact structure connected to the first conductive pattern and disposed between the first and second portions of the second conductive pattern.
Full Text
What is claimed is:
A semiconductor memory device of the technology, including: a lower structure; a first stacked structure; and a second stacked structure, wherein the first stacked structure includes at least one lower cell plug pattern extending in a vertical direction and a lower slit pattern extending in the vertical direction, and wherein the first stacked structure further includes: a first conductive pattern; a second conductive pattern over the first conductive pattern, wherein the second conductive pattern includes a first portion and a second portion; and a contact structure connected to the first conductive pattern and disposed between the first and second portions of the second conductive pattern.
Timeline
Filed
03/26/2026Published
07/30/2026Granted
Not AvailableIPC Codes(8)
H10B 80/00:Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10B 41/27:the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35:with a cell select transistor, e.g. NAND