PCIe UIO is defined for Flit Mode and requires the entire path from requester to completer to support UIO and Flit Mode. This constraint prevents UIO-capable entities from accessing resources at non-UIO entities and prevents UIO transactions from traversing split Flit Mode/Non-Flit Mode paths. Some implementations provide methods and systems for translating between PCIe UIO TLPs and non-UIO TLPs. A computer between a first entity and a second entity may receive a first PCIe Memory Read request, translate it to a second PCIe Memory Read request wherein one comprises a UIO Memory Read (e.g., UIOMRd) and the other comprises a non-UIO Memory Read (e.g., MRd), receive a PCIe Completion, translate it, and send it to the first entity. The translations may include address translation between different physical address spaces, enabling UIO to reach beyond standard PCIe path constraints, and may support split Flit Mode/Non-Flit Mode paths