For UALink and NVLink fabric deployments, a device coupled to a host via a CXL link exposes a first memory region via a first CXL device type flow and a second memory region via a second CXL device type flow, wherein the two flows differ. The first memory region is associated with a first memory, and the second memory region is associated with a second memory accessible via a different protocol, such as a UALink-based protocol or an NVLink-based protocol. The device translates between a CXL-based protocol and the different protocol for requests targeting at least one of the memory regions, enabling host access to local and remote memory through a CXL link. The different CXL device type flows may correspond to different coherency models, such as device-coherent and host-only-coherent, enabling differentiated memory access semantics across protocol boundaries, which enables accessing distributed accelerator memory pools spanning UALink or NVLink fabrics.