An apparatus includes: an interface comprising a first signal path and a second signal path coupled to a memory device; a controller configured to: determine a memory selection configuration represented by a plurality of bits; drive the first signal path, within a first time unit interval, to a state indicating a memory selection operation associated with the plurality of bits; drive the first signal path, within a second time unit interval consecutive to the first time unit interval, to an encoded state indicating a first bit of the plurality of bits; and drive the second signal path to an encoded state indicating a second bit of the plurality of bits within the first time unit interval or the second time unit interval.