A semiconductor package includes a first semiconductor chip, and at least one second semiconductor chip on the first semiconductor chip, the at least one second semiconductor chip including a substrate, an integrated device layer on the substrate, a multi-wiring layer on the integrated device layer having at least two layers of wires, and a pad metal layer on the multi-wiring layer, electrically connected to the wires, having test pads, pad metal layers including the pad metal layer arranged in a first direction parallel to a top surface of the semiconductor substrate or a second direction perpendicular to the first direction, and a test pad includes a central portion of the pad metal layer, the test pad is exposed by a protective layer that overlaps the pad metal layer, in a third direction perpendicular to the top surface of the semiconductor substrate, the wires disposed without overlapping the test pads.