/Method Of Manufacturing Semiconductor Device Including Forming Source/drain Region
Abstract

A method for manufacturing a semiconductor device includes forming a stacked structure by alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a substrate, forming an active region by partially removing the stacked structure and the substrate, forming a sacrificial gate structure to traverse the active region on the substrate and gate spacer layers on sidewalls of the sacrificial gate structure, forming a recess region by partially removing the stacked structure exposed from the sacrificial gate structure, forming a source/drain region in the recess region, forming an interlayer insulating layer covering the source/drain region, removing the sacrificial gate structure, removing the plurality of sacrificial layers, and forming a gate structure including a gate electrode layer in regions in which the sacrificial gate structure and the plurality of sacrificial layers are removed.

Full Text

What is claimed is:

A method for manufacturing a semiconductor device includes forming a stacked structure by alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a substrate, forming an active region by partially removing the stacked structure and the substrate, forming a sacrificial gate structure to traverse the active region on the substrate and gate spacer layers on sidewalls of the sacrificial gate structure, forming a recess region by partially removing the stacked structure exposed from the sacrificial gate structure, forming a source/drain region in the recess region, forming an interlayer insulating layer covering the source/drain region, removing the sacrificial gate structure, removing the plurality of sacrificial layers, and forming a gate structure including a gate electrode layer in regions in which the sacrificial gate structure and the plurality of sacrificial layers are removed.
Timeline
Filed
04/01/2026
Published
07/30/2026
Granted
Not Available
IPC Codes(2)
H10D 62/10:Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
H10D 30/67:Thin-film transistors [TFT]