Abstract
A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.
Full Text
What is claimed is:
A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.
Timeline
Filed
03/26/2026Published
07/30/2026Granted
Not AvailableIPC Codes(3)
G06F 13/16:for access to memory bus (takes precedence G06F 13/28)
G06F 13/40:Bus structure
G06F 13/42:Bus transfer protocol, e.g. handshake; Synchronisation