A memory system includes a memory device and a memory controller. The memory device includes a first memory region for storing plural data entries, a second memory region for storing a parity entry associated with the plural data entries, a third memory region for storing at least one partial parity entry corresponding to at least one sub-group, each sub-group including a part of the plural data entries. The memory controller generates a first partial parity entry corresponding to a first sub-group among the at least one sub-group to store the first partial parity entry in the third memory region, generates a second partial parity entry corresponding to a second sub-group among the at least one sub-group, reads the first partial parity entry from the third memory region, and performs a logical operation on the first partial parity entry and the second partial parity entry to generate the parity entry.