/Computer Architecture Having Selectable, Parallel And Serial Communication Channels Between Processors And Memory
Abstract
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.
Full Text
What is claimed is:
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.
Timeline
Filed
04/10/2026Published
08/06/2026Granted
Not AvailableIPC Codes(5)
G06F 1/10:Distribution of clock signals
G06F 3/06:Digital input from, or digital output to, record carriers
G06F 13/16:for access to memory bus (takes precedence G06F 13/28)