Abstract
A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A ring is around individual of the channel-material strings in at least one of a lowest of the conductive tiers or a lowest of the insulative tiers. Individual of the rings have a top that is below all of the memory cells. Other embodiments are disclosed.
Full Text
What is claimed is:
A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A ring is around individual of the channel-material strings in at least one of a lowest of the conductive tiers or a lowest of the insulative tiers. Individual of the rings have a top that is below all of the memory cells. Other embodiments are disclosed.
Timeline
Filed
04/01/2026Published
08/06/2026Granted
Not AvailableIPC Codes(7)
H10D 62/17:Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10B 41/10:characterised by the top-view layout
H10B 41/27:the channels comprising vertical portions, e.g. U-shaped channels