/Semiconductor System For Performing Read-modify-write Operation
Abstract

A semiconductor system includes a controller outputting a clock, a chip selection signal, a command address, and data, and a semiconductor device performing an auto-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the auto-refresh operation, correcting an error of internal data stored therein by performing a read-modify-write operation instead of the auto-refresh operation when the auto-refresh operation is performed a first set number of times and storing the corrected internal data, performing a self-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the self-refresh operation, and correcting an error of the internal data stored therein by performing a read-modify-write operation instead of the self-refresh operation when the self-refresh operation is performed a second set number of times and to store the corrected internal data.

Full Text

What is claimed is:

A semiconductor system includes a controller outputting a clock, a chip selection signal, a command address, and data, and a semiconductor device performing an auto-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the auto-refresh operation, correcting an error of internal data stored therein by performing a read-modify-write operation instead of the auto-refresh operation when the auto-refresh operation is performed a first set number of times and storing the corrected internal data, performing a self-refresh operation when the chip selection signal and command address input in synchronization with the clock have a combination for performing the self-refresh operation, and correcting an error of the internal data stored therein by performing a read-modify-write operation instead of the self-refresh operation when the self-refresh operation is performed a second set number of times and to store the corrected internal data.
Timeline
Filed
04/02/2026
Published
08/06/2026
Granted
Not Available
IPC Codes(3)
G11C 11/406:Management or control of the refreshing or charge-regeneration cycles
G11C 29/12:Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/46:Test trigger logic