/Phase Mixer Circuit, A Phase Mixing Method, And A Clock Generation Circuit And A Semiconductor Apparatus
Abstract
A phase mixer circuit is configured to receive a first input clock signal and a second input clock signal, and to generate an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals. The phase mixer circuit is configured to determine a logic value of a mixed code signal, and to generate an output clock signal by mixing one of the first and second input clock signals and the intermediate clock signal.
Full Text
What is claimed is:
A phase mixer circuit is configured to receive a first input clock signal and a second input clock signal, and to generate an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals. The phase mixer circuit is configured to determine a logic value of a mixed code signal, and to generate an output clock signal by mixing one of the first and second input clock signals and the intermediate clock signal.
Timeline
Filed
04/01/2026Published
08/06/2026Granted
Not AvailableIPC Codes(4)
H03K 5/02:by amplifying (takes precedence H03K 5/04)
H03K 3/037:Bistable circuits
H03K 5/135:by the use of time reference signals, e.g. clock signals