/Edge Server With Deep Learning Accelerator And Random Access Memory
Abstract

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be implemented using an integrated circuit device having: a Deep Learning Accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of a server application executable by a Central Processing Unit; and an interface to a communication device on a computer network. The Central Processing Unit may be part of the integrated circuit device, or be connected to the integrated circuit device. The server application may be configured to provide services over the computer network based on output of the Artificial Neural Network and input received from one or more local devices via a bus, or a wired or wireless local area network.

Full Text

What is claimed is:

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be implemented using an integrated circuit device having: a Deep Learning Accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of a server application executable by a Central Processing Unit; and an interface to a communication device on a computer network. The Central Processing Unit may be part of the integrated circuit device, or be connected to the integrated circuit device. The server application may be configured to provide services over the computer network based on output of the Artificial Neural Network and input received from one or more local devices via a bus, or a wired or wireless local area network.
Timeline
Filed
04/08/2026
Published
08/06/2026
Granted
Not Available
IPC Codes(5)
H04L 67/10:in which an application is distributed across nodes in the network (multiprogramming arrangements G06F 9/46; software deployment G06F 8/60)
G06F 9/30:Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F 9/22)
G06F 9/38:Concurrent instruction execution, e.g. pipeline or look ahead